1. Field of the Invention
The present invention relates to a redundancy enable circuit capable of achieving an increase in repair efficiency, and more particularly to a redundancy enable circuit for option-processing input addresses in accordance with a refresh option.
2. Description of the Prior Art
For option-processing of input addresses in accordance with a refresh option, a variety of refresh specifications are needed due to the compatibility required in dynamic random access memories (DRAMs) of 4M grade or greater with other grades, for example, the compatibility of 4M grade with 1M grade and the compatibility of 16M grade with 4M grade. Problems associated with power consumption involved in DRAMs also increase the variety of refresh specifications required.
By way of example, in the case of a 16M.times.1 DRAM and a 4M.times.4 DRAMs an option of 2 Kcycle/32 ms, which is the reference refresh of the 16M DRAM, is used. In such a case, an option of 4 Kcycle/64 ms is also used in order to reduce the power consumption. For a case of an 1M.times.16 DRAM, the option of 2 Kcycle/32 ms which is the reference refresh of the 16M DRAM is used. In order to reduce the power consumption in this case, the option of 4 Kcycle/64 ms is also used. In this case, an option of 1 Kcycle/16 ms is also used for the compatibility with the 4M DRAM. The refresh specification selected in the manner mentioned above, is called a "refresh option".
Referring to FIG. 1 and Table 1, there are illustrated a conventional redundancy circuit and a mapping relation of addresses selected depending on a refresh option.
As shown in FIG. 1, the redundancy enable circuit usable for conventional DRAMs of 16M grade uses block selecting row addresses RA89AB and column addresses AY0 to AY7.
When a global decoder is used, the redundancy circuit cuts off fuses of block selecting row addresses and those of addresses in a block respectively corresponding to failed column addresses. For example, where a 4K refresh option is generated, the refresh circuit cuts off fuses of block selecting addresses RA89 and RAAB and those of column addresses AY0 to AY7 respectively corresponding to failed block addresses RA89AB. For a 2K refresh option, the refresh circuit cuts off fuses of block selecting row addresses RA89 and RAAB and failed ones of column addresses AY0 to AY7 because the block selecting addresses are RA89A and the column addresses are AY0 to AY8.
TABLE 1 __________________________________________________________________________ RA89 RA89 RA89 RA89 RAAB RAAB RAAB RAAB AY0 AY0 AY1 __________________________________________________________________________ 4K RA89 RA89 RA89 RA89 RAAB RAAB RAAB RAAB AY0 AY0 AY1 Option 2K RA89 RA89 RA89 RA89 RAAB RAAB RAAB RAAB AY0 AY0 AY1 Option __________________________________________________________________________ AY1 AY2 AY2 AY3 AY3 AY4 AY4 AY5 AY5 AY6 AY6 AY7 AY7 __________________________________________________________________________ 4K AY1 AY2 AY2 AY3 AY3 AY4 AY4 AY5 AY5 AY6 AY6 AY7 AY7 Option 2K AY1 AY2 AY2 AY3 AY3 AY4 AY4 AY5 AY5 AY6 AY6 AY7 AY7 Option __________________________________________________________________________
Referring to FIG. 2, it can be found that the repair efficiency is reduced by 1/2 because the block selection is achieved only by RA89A of block selecting addresses RA89AB.
As a result, the conventional redundancy enable circuit involves a problem of a degraded repair efficiency because the conventional repair is achieved by constantly using all addresses transmitted from the redundancy circuit to the repair fuse box irrespective of the refresh option.